The present invention relates to software tools for facilitating automated verification of microchip designs. More specifically, the present invention relates to an integrated design verification methodology which employs software design tools to effect an automated verification of wire bond padring bond pad layouts based on a predefined set of design rules.
In the designing of microchips, there are many critical stages to ensure a complete integration and compliance of design parameters that will aid in effecting a reliable transition between the different manufacturing processes involved in the microchip fabrication. For example, a designer typically is given a set of predefined padring design rules for the verification of wire bond padring bond pad layouts. The padring design rules generally set limits on the bond pads' position on the padring according to a corresponding die mask, which may depend on a particular chip design family. These limits are usually defined by the packaging group and used by the designer for verification before the microchip enters the packaging stage. In the past, the designer would conduct the design verification process by manually measuring the bond pad positions one by one and comparing the results to the set of predefined padring design rules. Once a violation is found, as when a measurement does not conform to the padring design rules, the designer takes note of it by writing the violation down into a notebook.
To aid a designer in the verification of each wire bond padring, there are a number of commercially available software design tools. Computer aided design (CAD) tools, such as AutoCAD® by Autodesk, Inc. of San Rafael, Calif., provides an integrated measuring feature that, when selected, allows the designer to perform a single measurement of the distance between two points on an electronic drawing illustrative of the wire bond padring. This single measurement is performed after clicking with a mouse onto two corresponding points of interest located on the drawing.
There are problems associated with using an integrated measuring feature as provided in current software design tools to perform the verification of wire bond padrings. One problem is that one or both of the two points is sometimes not readily available on the drawing for this feature to be used. That is, the points may need further drafting to actually define the points since the drawing originally includes minimal information, typically providing only a scaled electronic outline of an actual wire bond padring. For example, in order to use the center of an eight sided closed polygon shaped bond pad as one of the points for the measurement, a designer will need to specially draw onto the drawing intersecting centerlines for the eight sided closed polygon shaped bond pad.
Another problem associated with using an integrated measuring feature as provided in current software design tools is the lack of consistent accuracy rendered by the end user, the designer in the case of wire bond padring verification. Since a designer must literally pick each point of interest by using a mouse, the accuracy of retrieving the correct measurement is subject to where on the drawing he clicks his mouse. For example, if the designer wants to measure the distance between two specific endpoints of two separate lines, he may instead click onto points near the endpoints without knowing that the actual endpoints were not chosen. Therefore, an inaccurate measurement would result in an incorrect measurement of the specific endpoints. Although some software design tools provide object snapping capabilities, a feature that allows the automatic selection of certain object features as points of interest, these are also subject to the lack of consistent accuracy rendered by the designer. This is because it again depends on where the designer clicks his mouse and whether there are more than one of the same feature in the object being snapped upon. Again in measuring the distance between two specific endpoints of two separate lines, for example, the designer may instead click his mouse onto a portion of either of the two lines that automatically selects the other endpoint of the same line rather than his intended endpoint for measurement. Accordingly, an inaccurate measurement results in an incorrect measurement of the specific endpoints.
Furthermore, current software design tools lack the capability to systematically and efficiently handle the increasingly high number of wire bond padring verifications, especially when such verifications need to be done accurately and completely. As integrated circuits have become smaller in size and denser, the number of bond pads has accordingly increased. The aforementioned integrated measurement feature provided by software design tools only allows a designer to perform a single manual measurement at a time. With the current number of bond pads varying between 100 to 800 per microchip and having a possibility of up to six measurements per bond pad, wire bond padring verification has become a very tedious and mistake prone task involving significant resources in terms of manpower and time.
In addition, this task is often done randomly in a sampling fashion in order to keep up with the changing demands of other manufacturing processes and overall production throughput. That is, the designer often just randomly samples a few bond pads per wire bond padring for verification rather than verifying that every bond pad is in compliance. Due to the possible missed violations of the predefined set of design rules, this random sampling method has the potential to result in the costly repetition of the manufacturing processes involved in microchip fabrication.
It is therefore desirable to provide a design verification methodology and associated design tools with which a designer may efficiently and automatically verify wire bond padring bond pad layouts based on a predefined set of design rules.